Today's networked computing environments are used in businesses for generating and storing large amounts of critical data. The systems used for moving, storing, and manipulating this critical data are expected to have high performance, high capacity, and high reliability, while being reasonably priced and having reasonable power consumption and electromagnetic interference (EMI) characteristics.
Early low-power circuits employed full-voltage-swing signaling. For example, a complementary metal-oxide-semiconductor (CMOS) output can swing from ground to the power-supply voltage, such as 0-5 or 0-3 volts. However, as signal speeds increase, unwanted EMI is increasingly generated, and signal quality deteriorates due to reflections, ringing, and voltage undershoot.
Reducing the voltage swing reduces these undesirable effects. However, noise margin is also reduced as the voltage swing is cut. Noise margin can be improved by using two signal wires to transmit a logical signal, rather than just one wire. Such differential signaling has been used for many years in bipolar emitter-coupled logic (ECL) systems.
More recently, the benefits of differential ECL signaling and low-power CMOS have been combined in what is known as pseudo-emitter-coupled logic (PECL). PECL uses differential signaling and current-steering through CMOS transistors. Data rates of 1 Gigabit per second and higher are desired.
FIG. 1A shows a differential signaling scheme. Driver 910 drives lines Y1, Y2 with opposite data. Current is steered among lines Y1, Y2 so that the amount of current passing through each of resistors 914 varies with the data. The I*R voltage drop across resistors 914 can be sensed by receiver 912. The other terminal of resistors 914 is connected to terminating voltage VTT.
FIG. 1B highlights the reduced voltage swing of differential signaling. Lines Y1, Y2 are driven to opposite states, depending on the data transmitted. The logic high level is reached when Y1 is driven to a VOH voltage, while the complement line Y2 is driven to a VOL level. For the logic low level, Y1 is driven to the VOL voltage, while the complement line Y2 is driven high to a VOH level.
To minimize EMI radiation and signal distortion, VOH and VOL are chosen to be close to each other. This minimizes the voltage swing from VOL to VOH. For example, VOL can be set to 1.66 volts, while VOH is set to 2.33 volts in systems with 3-volt supplies. The signal swing is thus reduced to about 700 mV. The terminating voltage VTT can be set to 2 volts below Vcc, or about 1.3 volts. This is below both VOH and VOL.
When 50-ohm terminating resistors are used for lines Y1, Y2, the amount of current to produce the desired VOH and VOL levels can be calculated using Ohm's law. The current switched is I=V/R=0.33v/50=6.6 mA.
Electronic signaling within and between integrated circuits (ICs) is accomplished using PECL and many other different formats, standards, and approaches. Each of these electronic signaling types may be based on and/or reflect a voltage range or swings thereof, an absolute current or changes thereto, a signaling speed or frequency modulation, a combination thereof, and so forth. The various circuits that are used to implement such different electronic signaling types are equally diverse, and may include, for example, signal transmitters or receivers.
Another example of such diverse circuit types for implementing the different electronic signaling types is Peripheral Control Interface (PCI) Express circuitry. (PCI Express is described in the PCI-SIG document “PCI Express Base Specification 1.0a” and accompanying documentation.)
The standard bus for computer peripherals has evolved from the early ISA interface, EISA interface, PCI33 interface, to PCI66 interface and PCI133 interface. The PCI associated peripheral devices prevail in recent years.
The PCI Express interface is becoming the standard interface of the next generation. PCI Express applies to point-to-point transmission. For each end point, each PCI Express lane has a signal transmission pair and a signal receiving pair. PCI express data transceiving requires four physical signals, and a plurality of control signals. The PCI Express specification defines the termination state of the receiver and the transmitter, including impedance, and common mode voltage, etc.
PCI Express devices employ differential drivers and receivers at each port. A positive voltage difference between a driver's terminals implies Logical 1. A negative voltage difference between the driver's terminals implies a Logical 0. No voltage difference between the driver's terminals means that the driver is in the high-impedance tristate condition. The PCI Express differential peak-to-peak signal voltage at the transmitter ranges from 800 mV-1200 mV, while the differential peak voltage is one-half these values. The common mode voltage can be any voltage between 0 V and 3.6 V. The differential driver is DC isolated from the differential receiver at the opposite end of the link by placing a capacitor at the driver side of the link. Two devices at opposite ends of a link may support different DC common mode voltages. The differential impedance at the receiver is matched with the board impedance to prevent reflections from occurring.
FIG. 2 illustrates a transmitter 110 that communicates over a PCI-Express link 150 with a receiver 170; link 150 is a differential transmission line. AC coupling between the transmitter 110 and receiver 170 is provided by coupling capacitors 160. As shown in FIG. 2, the transmitter 110 includes a pair of resistors 115, 120 between the differential transmission line 150 and ground. Similarly, the receiver 170 includes a pair of resistors 175, 180 between the differential transmission line 150 and ground. The resistors 115, 120, 175, 180 terminate the differential transmission line 150 to avoid reflections at higher speeds. The resistors 115, 120, 175, 180 typically have resistance values on the order of 50 Ohms.
For PECL signaling on a high-speed serial link for example, a high voltage swing is typically employed. Also, the common mode voltage set is typically far above zero volts. However, for PCI Express signaling, the signal input receiver is specified to have a zero volt termination. In other words, for PCI Express signaling, the signal common mode voltage on the receiving side of coupling capacitors is to be maintained at zero volts.
In at least some applications, PECL technology accepts a 600 mv swing centered around a 2 volt offset, and PCI Express technology accepts 700 mv as Vhigh and 300 mv as Vlow.